1. Field of the Invention
The present invention relates to reducing the power consumption of a memory unit, and particularly, to a low-power-consumption memory unit and a microprocessor that employs such a memory unit and is suitable for use with portable apparatus.
2. Description of the Prior Art
Various types of portable apparatus are widely used. They must operate for a long time with batteries, and therefore, semiconductor memories incorporated therein must operate at low power consumption. The portable apparatus also needs a high-speed microprocessor. To improve performance and reduce power consumption, the microprocessors employ a cache memory that helps reduce the number of access operations with respect to a main memory.
FIG. 1 shows a microprocessor 101 incorporating a cache memory 102, according to a prior art. The cache memory 102 has an address decoder 103 for decoding an address provided by a CPU 190, a tag memory cell array 104 for storing tag data that is accessed with the decoded address, a data memory cell array 105 for storing data related to the tag data stored in the array 104, a conventional read/write circuit 106 for reading and writing data from and to the array 104, a comparator unit 107 for comparing tag data that is read out of the array 104 through the conventional read/write circuit 106 with a tag address that is a part of the address provided by the CPU 190 and determining whether they agree (hit) or disagree (miss) with each other, and a conventional read/write circuit 108 for reading and writing data from and to the array 105. The microprocessor 101 has a cache controller 109 for controlling the cache memory 102, and a bus interface unit 110 serving as an interface with respect to an external memory 200.
The CPU 190 provides a memory access request that includes an address where data must be read. Lower bits of the address are supplied to the address decoder 103 and are used to access the tag memory cell array 104 and data memory cell array 105. The accessed memory cells of the arrays 104 and 105 provide each a minute voltage signal of about 100 mV to the respective conventional read/write circuits 106 and 108. The read/write circuits 106 and 108 amplify the minute voltage signal and generate data. The comparator unit 107 compares the read tag data with a tag address represented with higher bits of the address contained in the memory access request provided by the CPU 190. If the comparator unit 107 determines that they agree with each other, the data memory cell array 105 has the requested data, and therefore, the data read out of the data memory cell array 105 is transferred to the CPU 190. If the comparator unit 107 determines that they disagree with each other, the data memory cell array 105 does not have the requested data, and therefore, the cache controller 109 provides the bus interface unit 110 with an access request for the external memory 200.
To improve system performance, the cache memory 102 must hold frequently accessed data. For this purpose, the data transferred from the external memory 200 to the CPU 190 is simultaneously stored in the cache memory 102 under the control of the cache controller 109. This operation is called a refill operation. In the refill operation, the tag address of the accessed address and the data read out of the external memory 200 are written into the arrays 104 and 105 through the conventional read/write circuits 106 and 108.
FIG. 2 shows examples of the conventional read/write circuit 106 and comparator unit 107 of the tag memory cell array 104. The conventional read/write circuit 106 has, for every bit-line pair that consists of a pair of bit lines BL and BL, a write circuit 111 for writing tag data and a sense amplifier 112 for amplifying tag data read through the bit lines BL and BL. The comparator unit 107 has a comparator 113 provided for every bit-line pair, for comparing a tag address provided by the CPU 190 with tag data read by the sense amplifiers 112, and a hit/miss logic 114 for receiving comparison results from the comparators 113 and determining whether or not the tag address agrees with the tag data.
When the cache memory 102 is accessed, a sense amplifier enable signal becomes active to make each sense amplifier 112 amplify a minute voltage signal sent from a memory cell through the bit lines BL and BL. The amplified minute voltage signal from each sense amplifier 112 represents one bit of tag data, which is compared by the comparator 113 with a corresponding bit of a tag address. Comparison results of the comparators 113 are supplied to the hit/miss logic 114. If the tag data agrees with the tag address bit by bit, the hit/miss logic 114 provides a hit signal, and if not, a miss signal. The hit or miss signal is sent to the cache controller 109.
If the hit signal is provided, data read out of the data memory cell array 105 at the instant is sent as it is to the CPU 190, and the cache memory access completes. On the other hand, if the miss signal is provided, an access request for the external memory 200 is made by the cache controller 109. When the requested data is read out of the external memory 200, a refill operation starts. In the refill operation, a write enable signal becomes active to make the write circuits 111 provide the bit-line pairs with tag data to be written into the tag memory cell array 104.
FIG. 3 shows an example of one of the write circuits 111. Transfer gates 115 and 116 connect the bit lines BL and BL to write buffers 117 and 118, respectively. The transfer gates 115 and 116 are opened and closed in response to write enable signals EN and EN. The write buffers 117 and 118 buffer data to be transferred to the bit lines BL and BL through the transfer gates 115 and 116. When writing data, the transfer gates 115 and 116 become conductive, and the write buffers 117 and 118 fully swing the bit lines BL and BL between predetermined source voltages.
The conventional read/write circuit 108 of the data memory cell array 105 has the same structure as the conventional read/write circuit 106 of the tag memory cell array 104. The conventional read/write circuit 108, however, is not provided with the comparator unit 107, and therefore, data read out of the data memory cell array 105 is directly provided outside, and data to be written into the data memory cell array 105 is provided by the external memory 200.
In the refill operation of the cache memory 102, every bit line of the arrays 104 and 105 is subjected to a write operation. The write operation fully swings each bit line between a high level supply voltage and a low level supply voltage. Since the bit lines have load such as wiring capacitance and transistor junction capacitance, the full-swing write operation consumes a lot of electric power compared with a read operation that involves the minute voltage signal and a small current. In a low-power-consumption cache memory, currents produced by the charging and discharging of bit lines reach about a half of the power consumption of the refill operation. As a result, the power consumption of the refill operation is about 30% larger than that of any other access operation. A store operation (a write operation) also consumes a lot of electric power because it involves a write operation of a data bit width.
This large power consumption problem occurs not only in the cache memories but also in other types of memories. Namely, a current consumed by a write operation is larger than a current consumed by a read operation because the write operation fully swings bit lines between the high and low level supply voltages to charge and discharge the wiring capacitance and transistor junction capacitance.
More precisely, the prior art writes data by fully swinging bit lines for a supply voltage of 5 V, 3.2 V, 2 V, or 1.5 V. This involves large power consumption compared with a read operation that needs only a minute voltage of about 100 mV. This is the reason why it is difficult to reduce the power consumption of a cache memory although the portable apparatus that uses the cache memory is required to operate at low power consumption.